The present invention relates in general to semiconductor technology, and more particularly to techniques for controlling the trench profile in semiconductor structures.
In many semiconductor structures, trenches of varying depths and widths that subsequently are partially or completely filled with various materials need to be formed. For example, in power device technology, trenches are formed for various purposes. In trench-gate power MOSFETs, trenches housing the gate electrode are formed; in shielded gate power MOSFETs, deeper trenches housing both a shield electrode and a gate electrode are formed; in yet other types of power devices which include what is commonly referred to as charge balance alternating p-n pillars structure, even deeper trenches are formed and subsequently filled with silicon material to form the alternating p-n pillars. In order to form the trenches in these structures, various silicon etch processes such as a dry etch process are used. However, as the critical dimensions (CD) continue to shrink, the width of the trenches is reduced while the depth of the trenches is not changed, or in some cases is increased. An aspect ratio of depth/width of the trenches is thus increased. The increasing aspect ratio of the trenches may adversely affect the filling of the trenches with such materials as gate polysilicon, epi material or dielectric material. Some common problems are formation of gaps, voids and/or defects in the filling material, which can adversely impact the device performance characteristics. Methods such as wet etch processes have been proposed to obtain trenches with wider upper portions, however, the wet etch process is an isotropic process and difficult to control.
Accordingly, there is a need for techniques which provide precise control over the trench profile, particularly for mid to high aspect ratio trenches.